Bài giảng Electronic circuits - Chapter 4: Multistage amplifier and differential amplifier - Trịnh Xuân Dũng
Dr. Dung Trinh
HCMUT / 2017
Electronic Circuits
Chapter 4: Multistage Amplifier and
Differential Amplifier
Dr. Dung Trinh
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Dr. Dung Trinh
HCMUT / 2017
Content
Introduction
Cascade Configuration
Cascode Configuration
Darlington Configuration
Differential Amplifier
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Dr. Dung Trinh
HCMUT / 2017
Introduction
In most applications, a single
transistor amplifier will not be
able to meet the combined
specifications of a given
amplification
factor,
input
resistance, and output resistance.
A generalized three-stage amplifier
BJT
Name
Comments
2nd stage
1st stage
Voltage Amp
Cascode
CE
CE
CE
CB
CB
CB
CC
CC
CC
CE
CB
CC
CC
CE
CB
CE
CB
CC
High Voltage Gain
High bandwidth
Op-Amp
High Zin low Zout
Higher Zout than CB/CG
Current buffer
Current buffer
Not common
Not common
Differential Amp
Darlington
High voltage gain and BW.
High current gain
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Dr. Dung Trinh
HCMUT / 2017
Cascade Configuration
A two-stage common-emitter amplifier in a cascade
configuration with npn and pnp transistors
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Dr. Dung Trinh
HCMUT / 2017
Cascade Configuration
Two stage common-emitter amplifier in a cascade configuration:
small signal equivalent circuit.
Input resistance: 푹풊풏 = 푹ퟏ ∥ 푹ퟐ ∥ 풓흅ퟏ
Small signal voltage gain:
푹ퟏ ∥ 푹ퟐ
푨풗 = 품풎ퟐ 푹ퟐ ∥ 푹푳 품풎ퟏ 푹푪ퟏ ∥ 풓흅ퟐ
푹ퟏ ∥ 푹ퟐ + 푹풔
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Dr. Dung Trinh
HCMUT / 2017
Cascade Configuration
Example 1: Determine the small-signal voltage gain of the following multi-transistor
circuit:
1 = 173
ICQ1 = 2.54 mA
2 = 157
ICQ2 = 1.18 mA
VC1
= -0.82 V
VECQ1 = 1.10 V
VCEQ2 = 1.79 V
GV = 4790
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Dr. Dung Trinh
HCMUT / 2017
Cascade Configuration
Example 1: Determine the small-signal voltage gain of the following multi-transistor
circuit:
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Dr. Dung Trinh
HCMUT / 2017
Cascade Configuration
Example 1: Determine the small-signal voltage gain of the following multi-transistor
circuit:
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HCMUT / 2017
Cascade Configuration
Example 2: Consider the circuit shown in the following figure. The transistor parameters
are 푘푛1 = 0.5mA/푉2, 푘푛2 = 0.2mA/푉2and 푉푇푁1 = 푉푇푁2 = 1.2푉. The Q point is: 퐼퐷1 =
0.2푚퐴, 퐼퐷2 = 0.5푚퐴.
Determine the small-signal voltage gain of a multistage cascade circuit.
Gv = -6.14
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Dr. Dung Trinh
HCMUT / 2017
Cascade Configuration
Exercise 1: Consider the circuit shown in the following figure. The transistor parameters
are = 125, 푉퐵퐸(표푛) = 0.7푉
a. Determine the small-signal voltage gain of the multistage cascade circuit.
b. Determine the input resistance and output resistance.
Gv = -17.7
Rin = 4.76 k
Ro
= 43.7
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Dr. Dung Trinh
HCMUT / 2017
Cascode Configuration
In cascode configuration, a Common-
Emitter (or Common-Source) amplifier
drives a Common-Base (or Common-
Gate) amplifier.
The input capacitance of CE amplifier is
small because the voltage gain of Q1 is
small (near unity) which means the
Miller capacitance is minimized.
The CE stage increases the input
impedance of the CB stage.
Cascode Amplifier
The voltage gain is achieve in the
Common-Base stage.
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Dr. Dung Trinh
HCMUT / 2017
Cascode Configuration
The ac equivalent circuit
Cascode Amplifier
The small-signal equivalent circuit
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HCMUT / 2017
Cascode Configuration
Example 2: Consider the circuit shown in the
following figure. The transistor parameters are
푘푛1 = 0.8mA/푉2 , 푘푛2 = 0.8mA/푉2 and 푉푇푁1
=
푉푇푁2 = 1.2푉. The Q point is: 퐼퐷1 = 0.4푚퐴, 퐼퐷2 =
0.4푚퐴.
Determine the small-signal voltage gain of the
cascode circuit.
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HCMUT / 2017
Cascode Configuration
PSPICE Simulation: Use PSPICE to run simulation for the following CE-CB (cascode) amplifier.
The Beta DC of Q1,Q2 are 162 and 161 respectively. The mid-band gain of the amplifier from
PSPICE is 120. Validate the DC and AC analysis of the amplifier using circuit analysis? Note that
Beta AC gain of Q1, Q2 are 177 and 176 respectively.
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Cascode Configuration
PSPICE Simulation: It is clear that the high-frequency (HF) 3dB cut-off frequency of the
Cascode amplifier is much higher than that of the circuit in Example 1 (CE-CE Amplifier).
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HCMUT / 2017
Darlington Pair
In some applications, it would be desirable to have a bipolar
transistor with a much larger current gain than can normally be
obtained.
A Darlington configuration provides increased current gain.
The effective 훽 of the Darlington pair is:
휷푫푷 = 휷ퟏ휷ퟐ + 휷ퟏ + 휷ퟐ
Darlington pairs are often fabricated on a
single chip to achieve matched Q1 and Q2
characteristics. Then:
휷푫푷 = 휷ퟐ + ퟐ휷
A Darlington pair configuration
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HCMUT / 2017
Darlington Pair
The effective small-signal input resistance
of the Darlington pair is:
푟
= 훽1 푟푒1 + 푟푖푛 푏푎푠푒 2 ≃ 훽1 푟푒1 + 훽2푟푒2
푖푛(퐷푃)
where:
25푚푉
25푚푉
푟푒1 =
푟푒2 =
퐼퐶1
퐼퐶2
Small-signal equivalent circuit
Note that: 퐼퐸2 ≃ 훽2퐼퐸1. Then: 푟푒1 ≃ 훽2푟푒2
≃ 훽1 푟푒1 + 훽2푟푒2 = 2푟푒2
푟
And:
푖푛(퐷푃)
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Darlington Pair
PSPICE Simulation: Use PSPICE to run simulation for the following CE-CC amplifier. The Beta
DC gain of Q1,Q2 and Q3 are 168, 187 and 108 respectively. The mid-band gain of the
amplifier from PSPICE is 26. Validate the DC and AC analysis of the amplifier using circuit
analysis? Note that Beta AC gain of Q1, Q2 and Q3 are 184, 197 and 126 respectively.
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HCMUT / 2017
Differential Amplifier
The input stage of every op amp is a differential amplifier.
Less sensitive to noise and interference.
Enable to bias amplifier and connect to other stage without the use of
coupling capacitors.
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HCMUT / 2017
Differential Amplifier – DC Analysis
Assume Q1 and Q2 are matched.
퐼푄
퐼퐸1 = 퐼퐸2 =
2
퐼푄
푣퐶1 = 푣퐶2 = 푉+ − 푅퐶
2
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