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Bài giảng Vi xử lý - Chương 3: Họ vi điều khiển 8051 - Tống Văn On

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CHƯƠNG 3  
HỌ VI ĐiỀU KHIỂN 8051  
Kiến trúc phần cứng 8051  
8051 Pin Diagram  
PDIP/Cerdip  
Vcc  
P1.0  
P1.1  
P1.2  
P1.3  
P1.4  
P1.5  
P1.6  
P1.7  
RST  
1
2
3
4
5
6
7
8
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
P0.0(AD0)  
P0.1(AD1)  
P0.2(AD2)  
P0.3(AD3)  
P0.4(AD4)  
P0.5(AD5)  
P0.6(AD6)  
P0.7(AD7)  
EA/VPP  
ALE/PROG  
PSEN  
P2.7(A15)  
P2.6(A14)  
P2.5(A13)  
P2.4(A12)  
P2.3(A11)  
P2.2(A10)  
P2.1(A9)  
P2.0(A8)  
8051  
(8031)  
9
(RXD)P3.0  
(TXD)P3.1  
(INT0)P3.2  
(INT1)P3.3  
(T0)P3.4  
(T1)P3.5  
(WR)P3.6  
(RD)P3.7  
XTAL2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
XTAL1  
GND  
Writing “1” to Output Pin P1.X  
Read latch  
Vcc  
TB2  
2. output pin is  
Load(L1)  
M1  
Vcc  
1. write a 1 to the pin  
1
P1.X  
pin  
D
Q
Internal CPU  
bus  
P1.X  
output 1  
0
Clk Q  
Write to latch  
TB1  
Read pin  
8051 IC  
Writing “0” to Output Pin P1.X  
Read latch  
Vcc  
TB2  
2. output pin is  
Load(L1)  
M1  
ground  
1. write a 0 to the pin  
0
P1.X  
pin  
D
Q
Internal CPU  
bus  
P1.X  
output 0  
1
Clk Q  
Write to latch  
TB1  
Read pin  
8051 IC  
Reading “1” at Input Pin  
Read latch  
2. MOV A,P1  
Vcc  
TB2  
1. write a 1 to the pin  
MOV P1,#0FFH  
external  
pin=High  
Load(L1)  
1
1
P1.X  
pin  
D
Q
Internal CPU  
bus  
P1.X  
0
M1  
Clk Q  
Write to latch  
TB1  
Read pin  
3. Read pin=1  
Read latch=0 Write  
to latch=1  
8051 IC  
Reading “0” at Input Pin  
Read latch  
Vcc  
2. MOV A,P1  
external  
TB2  
1. write a 1 to the pin  
Load(L1)  
MOV P1,#0FFH  
Internal CPU  
bus  
pin=Low  
1
0
P1.X  
pin  
D
Q
P1.X  
0
M1  
Clk Q  
Write to latch  
TB1  
Read pin  
3. Read pin=1  
Read latch=0 Write  
to latch=1  
8051 IC  
Instructions For Reading an Input Port  
• Following are instructions for reading external pins of ports:  
Mnemonics Examples  
Description  
Bring into A the data at P2  
pins  
MOV A,PX  
MOV A,P2  
JNB PX.Y,.. JNB P2.1,TARGET  
JB PX.Y,.. JB P1.3,TARGET  
Jump if pin P2.1 is low  
Jump if pin P1.3 is high  
MOV C,PX.Y MOV C,P2.4  
Copy status of pin P2.4 to CY  
Figure C-17. Reading the Latch  
1. Read pin=0 Read latch=1  
Write to latch=0 (Assume  
P1.X=0 initially)  
Read latch  
Vcc  
TB2  
Load(L1)  
2. CPU compute P1.X  
4. P1.X=1  
0
OR 1  
0
1
P1.X  
pin  
D
Q
Internal CPU  
bus  
P1.X  
1
M1  
Clk Q  
Write to latch  
3. write result to latch  
Read pin=0  
latch=0  
Read  
Write to  
TB1  
latch=1  
Read pin  
8051 IC  
Read-Modify-Write Instructions  
Mnemonics  
ANL  
Example  
ANL P1,A  
ORL P1,A  
XRL P1,A  
ORL  
XRL  
JBC PX.Y, TARGET JBC P1.1, TARGET  
CPL  
CPL P1.2  
INC  
INC P1  
DEC  
DEC P1  
DJNZ PX, TARGET  
MOV PX.Y,C  
CLR PX.Y  
SETB PX.Y  
DJNZ P1,TARGET  
MOV P1.2,C  
CLR P1.3  
SETB P1.4  
A Pin of Port 0  
Read latch  
TB2  
P0.X  
pin  
D
Q
Internal CPU  
bus  
P1.X  
M1  
Clk Q  
Write to latch  
TB1  
P1.x  
Read pin  
8051 IC  
Port 0 with Pull-Up Resistors  
Vcc  
10 K  
P0.0  
P0.1  
P0.2  
P0.3  
P0.4  
P0.5  
P0.6  
P0.7  
DS5000  
8751  
0
8951  
Reading ROM (1/2)  
2. 74373 latches  
1. Send address to  
the address and  
ROM  
send to ROM  
PSEN  
ALE  
OE  
OC  
74LS373  
G
P0.0  
P0.7  
A0  
A7  
D
Address  
D0  
D7  
EA  
P2.0  
P2.7  
A8  
A12  
8051  
ROM  
Reading ROM (2/2)  
2. 74373 latches  
the address and  
send to ROM  
PSEN  
ALE  
OE  
OC  
74LS373  
G
P0.0  
P0.7  
A0  
A7  
D
Address  
D0  
D7  
EA  
3. ROM send the  
instruction back  
P2.0  
P2.7  
A8  
A12  
8051  
ROM  
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