Bài giảng The 8051 Microcontroller - Chapter 2: Overview - Lê Chí Thông
ĐH Bách Khoa - ĐHQG TP.HCM
Lê Chí Thông - [email protected]
The 8051 Microcontroller
Chapter 2
Overview
Lê Chí Thông
Ref. I. Scott Mackenzie, The 8051 Microcontroller
Chapter 2: Overview
• Hardware Summary
• Address Decoder Summary
• First Program
• Simple Programs
• Instruction Set Summary
Ref. I. Scott Mackenzie
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Chapter 2: Overview
• Hardware Summary
• Address Decoder Summary
• First Program
• Simple Programs
• Instruction Set Summary
Ref. I. Scott Mackenzie
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Features of 8051
•
•
•
•
•
•
•
4KB ROM
128 bytes RAM
Four 8-bit I/O ports
Two 16-bit timers
Serial interface
64KB external code memory space
64KB external data memory space
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Comparison of MCS-51 Family
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8051 Block Diagram
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PORT 0
-
-
IO Port
Address/Data Bus
(A0 – A7) / (D0 – D7)
PORT 1: IO Port
PORT 3
PORT 2
-
-
IO Port
Control signals
-
-
IO Port
Address Bus
(A8 – A15)
FIGURE 2–2 80
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Around The Pins
• Port 0: dual purpose
o I/O port
o Multiplexed address and data bus (AD0-AD7)
• Port 1: I/O port
• Port 2: dual purpose
o I/O port
o High-byte address bus (A8-A15)
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• Port 3: dual purpose
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• /PSEN (Program Store Enable)
o Connects to /OE (Output Enable) of EPROM to permit
reading of program bytes
/PSEN (8051) ꢀ /OE (ROM)
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• ALE (Address Latch Enable)
o ALE (8051) ꢀ G (74373)
o Use to demultiplex the address and data bus
PORT 0 ꢀ D0 – D7 and A0 – A7
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IO Port – Data bus – Address bus
Port
No external memory
With external memory
Port 0
IO Port
Data bus D0 – D7
Address bus A0 – A7
Port 1
Port 2
Port 3
IO Port
IO Port
IO Port
Address bus A8 – A15
IO Port / Control Port
IO Port / Control Port
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• /EA (External Access) It is tied to +5V or ground.
o /EA = +5V: executes programs from internal ROM
o /EA = 0V: executes programs from external ROM
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• RST (Reset):
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• XTAL1 , XTAL2: On-chip oscillator inputs
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A machine cycle is 12 oscillator periods.
Use 12 MHz crystal: a machine cycle is 1 µs
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Machine Cycle
Internal clock fCLK = fCrystal / 12
Machine cycle MC = 12 / fCrystal
• Xtal 12 MHz ꢀ MC = 1 μs
• Xtal 6 MHz ꢀ MC = ? μs
ꢀ MC = 2 μs
• Xtal 24 MHz ꢀ MC = ? μs
ꢀ MC = 0.5 μs
Ref. I. Scott Mackenzie
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• Vdd, Vss: Power connections
o Vdd is connected to +5V
o Vss is connected to ground (0V)
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I/O Port Structure
• Port 1, 2, and 3 have internal pull-up resistors.
• Port 0 has no internal pull-up resistors.
• Instructions that input a port bit require the ‘1’ port latch.
Don’t need Bus-driver
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Memory Organization
• Memory
o ROM: for program (code) ꢀ Code memory
ꢁ External: maximum 64K
ꢁ Internal (on-chip): depend on chips
o RAM: for data ꢀ Data memory
ꢁ External: maximum 64K
ꢁ Internal (on-chip): depend on chips
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Memory Map
256-byte
Ref. I. Scott Mackenzie
64-Kbyte
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• Internal (on-chip) data memory
o Register banks (00H-1FH)
o Bit-addressable RAM (20H-2FH)
o General-purpose RAM (30H-7FH)
o Special function registers (80H-FFH)
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• Internal (on-chip) data memory:
General purpose
RAM
(30H-7FH)
Using for MUL,DIV
Bit-addressable
RAM
(20H-2FH)
Register banks
(00H-1FH)
DPTR
Special function
registers
(80H-FFH)
Ref. I. Scott Mackenzie
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Chapter 2: Overview
• Hardware Summary
• Address Decoder Summary
• First Program
• Simple Programs
• Instruction Set Summary
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Memory Organization
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External Memory
• Use external memory: need to create Data bus and
Address bus from Port 0 and Port 2
• Cannot use Port 0 and Port 2 as IO Port
D0 – D7
A0 – A7
A8 – A15
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External Memory
• 8051 usually uses ROMs as code memory and RAMs as
data memory.
• External Data Memory (External RAM)
o Pin connection: /RD ꢀ /OE; /WR ꢀ /W
o Instruction: MOVX
• External Code Memory (External ROM)
o Pin connection: /PSEN ꢀ /OE
o Instruction: MOVC
Ref. I. Scott Mackenzie
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External Data Memory (External RAM)
o Pin connection: /RD ꢀ /OE; /WR ꢀ /W
o Instruction: MOVX
o Port 0 is AD0-AD7 bus & Port 2 is A8-A15 bus.
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External Code Memory (External ROM)
o Pin connection: /PSEN ꢀ /OE
o Instruction: MOVC
o Port 0 is AD0-AD7 bus & Port 2 is A8-A15 bus.
/CS
Ref. I. Scott Mackenzie
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Address Decoding
• 1 RAM / 1 ROM / 1 RAM and 1 ROM:
no Address Decoder required
• ROM and RAM may have the same address.
RAM
ROM
/CS
/CS
Address of RAM:
0000H - FFFFH
Address of ROM:
0000H - FFFFH
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Address Decoding
• Multiple ROMs and/or RAMs are interfaced to an
8051: Address Decoder is required
RAM 2
RAM 1
A15
/CS
/CS
Address of RAM 1:
0000H - 7FFFH
Address of RAM 2:
8000H - FFFFH
Ref. I. Scott Mackenzie
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Address Decoding
• Typically, a decoder IC such as 74138 is used
with its outputs connected to the chip select (/CS)
inputs on the memory ICs.
ADDRESS DECODER
U7
A13
A14
A15
/CS0
/CS1
/CS2
/CS3
/CS4
/CS5
/CS6
/CS7
1
2
3
15
14
13
12
11
10
9
A
B
C
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
+5 V
6
4
5
G1
G2A
G2B
7
74LS138
Ref. I. Scott Mackenzie
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ADDRESS DECODER
Address
CS
U7
A13
A14
A15
/CS0
/CS1
/CS2
/CS3
/CS4
/CS5
/CS6
/CS7
1
2
3
15
14
13
12
11
10
9
0000H – 1FFFH
2000H – 3FFFH
4000H – 5FFFH
/CS0
/CS1
/CS2
…
A
B
C
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
+5 V
6
4
5
G1
G2A
G2B
7
E000H - FFFFH
/CS7
74LS138
74138
C
B
A
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
/CS0
/CS1
/CS2
0
0
0
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
…
1
/CS7
1
Ref. I. Scott1Mackenzie
X
X
X
X
X
LêXChí Thông
X
X
X
X
X
X
X
33
RAM
ROM
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ADDRESS BUS [A0-A15]
DATA BUS [D0-D7]
A0 – A15
D0 – D7
U2
U1
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
A8
A9
2
5
6
3
4
7
8
13
14
17
18
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
Q0
D0
D1
D2
D3
D4
D5
D6
D7
P0.0/AD0
P0.1/AD1
P2.0/A8
P2.1/A9
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A10
A11
A12
A13
A14
A15
P0.2/AD2 P2.2/A10
P0.3/AD3 P2.3/A11
P0.4/AD4 P2.4/A12
P0.5/AD5 P2.5/A13
P0.6/AD6 P2.6/A14
P0.7/AD7 P2.7/A15
9
12
15
16
19
ALE P1.0
P1.1
P1.2
RXD
TXD
/INT0
/INT1
T0
T1
/WR
/RD
11
1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
LE
OE
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
P1.3
P1.4
P1.5
P1.6
P1.7
74LS373
C1
ALE
/PSEN
19
18
30
29
X1
X2
ALE
PSEN
30 pF
C2
Y1
31
9
EA
RST
12 MHz
+5 V
40
VCC
8951
+5 V
+5 V
30 pF
C3
10 uF
R1
100
SW1
RESET
R2
8.2 k
Ref. I. Scott Mackenzie
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ROM 1
ROM 2
ROM
U3
2764
U4
2764
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
D0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
D0
D1
D2
D3
D4
D5
D6
D7
10
9
8
7
6
5
4
3
25
24
21
23
2
11
12
13
15
16
17
18
19
10
9
8
7
6
5
4
3
25
24
21
23
2
11
12
13
15
16
17
18
19
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
O0
O1
O2
O3
O4
O5
O6
O7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
O0
O1
O2
O3
O4
O5
O6
O7
D1
D2
D3
D4
D5
D6
D7
/PSEN
/PSEN
+5 V
22
27
20
+5 V
22
27
20
OE
PGM
CE
OE
PGM
CE
/CS0
/CS1
1
1
VPP
VPP
0000H-1FFFH
2000H-3FFFH
Ref. I. Scott Mackenzie
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RAM 1
RAM 2
RAM
U5
6264
U6
6264
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
D0
D1
D2
D3
D4
D5
D6
D7
10
9
8
7
6
5
4
3
25
24
21
23
2
11
12
13
15
16
17
18
19
10
9
8
7
6
5
4
3
25
24
21
23
2
11
12
13
15
16
17
18
19
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
D0
D1
D2
D3
D4
D5
D6
D7
/RD
/WR
/CS0
/RD
/WR
/CS1
22
27
20
26
22
27
20
26
OE
OE
WE
CS1
CS2
WE
CS1
CS2
+5 V
+5 V
0000H-1FFFH
2000H-3FFFH
Ref. I. Scott Mackenzie
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EXTRA OUTPUT PORTS
Extra Output Ports
Eg. To output 0FH to this port
MOV A,#0FH
U8
D0
D1
D2
D3
D4
D5
D6
D7
3
4
2
D0
Q0
5
MOV DPTR,#4000H
MOVX @DPTR,A
D1
D2
D3
D4
D5
D6
D7
Q1
6
7
8
Q2
9
Q3
12
13
14
17
18
Q4
15
ADDRESS: 4XXXH
Q5
16
Q6
19
U9A 74LS02
Q7
/CS2
/WR
2
3
1
11
1
LE
OE
74LS373
Eg. To output F0H to this port
MOV A,#0F0H
U10
D1
D2
D3
D4
D5
D6
D7
D8
3
4
2
D0
D1
D2
D3
D4
D5
D6
D7
Q0
5
MOV DPTR,#6000H
MOVX @DPTR,A
Q1
6
7
8
Q2
9
Q3
12
13
14
17
18
Q4
15
ADDRESS: 6XXXH
Q5
16
Q6
19
U9B 74LS02
Q7
/CS3
/WR
5
6
4
11
1
LE
OE
74LS373
Ref. I. Scott Mackenzie
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+5 V
EXTRA INPUT PORTS
Extra Input
Ports
10 K
Eg. To input from this port
MOV DPTR,#4000H
U11
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
18
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
MOVX A,@DPTR
17
16
15
14
13
12
11
ADDRESS: 4XXXH
U12A 74LS32
/CS2
/RD
1
2
1
19
+5 V
DIR
G
3
74LS245
10 K
Eg. To input from this port
MOV DPTR,#6000H
U13
D1
D2
D3
D4
D5
D6
D7
D8
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
MOVX A,@DPTR
ADDRESS: 6XXXH
U12B 74LS32
/CS3
/RD
4
5
1
19
DIR
G
6
74LS245
Ref. I. Scott Mackenzie
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• Overlapping the External Code and Data Spaces
o A RAM can occupy code and data memory space by
using the following circuit.
For external CODE and DATA memory
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